Fin field-effect transistors (FinFETs) are double-gate transistors built on an SOI/bulk semiconductor substrate. In implementation, the gate is wrapped around the channel of the FET, forming a double gate structure. More particularly, in a conventional FinFET a portion of the silicon has been etched into a thin, “fin”-like shape. That is, a narrow body of silicon with channels on each side is formed on a wafer, such as a silicon oxide insulating (SOI) wafer. A gate electrode is applied to the “fin” such that it wraps around on two or more sides.
The FinFET device has significantly better control of short channel effect and higher or equivalent current density than conventional CMOS technologies, and may be used in almost all types of integrated circuit designs (i.e., microprocessors, memory, etc.). Specifically, the use of the double gate suppresses Short Channel Effects (SCE), provides for lower leakage, provides for more ideal switching behavior, and reduces power consumption. In addition, the use of the FinFET increases gate area, which allows the FinFET to have better current control, without increasing the gate length of the device. As such, the FinFET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
In fabrication processes, conventional ion extension implants and halo implants are used to implant dopants in the source/drain (S/D) region of the device. For example, a halo implant is a fabrication step which involves the doping of regions beneath the lightly-doped source/drain (S/D) extension regions of the transistor so as to form halo regions. For each of such halo regions, only the portion under the gate region (called undercutting portion) is useful, and therefore desirable, whereas the rest of the halo region has the effect of reducing the doping concentration of the respective S/D region (called the S/D doping reduction effect), which is undesirable.
The conventional extension and halo implantation process, though, may cause some undesirable effects on the FinFET. For example, the extension and halo implants may result in straggle. Straggle is the lateral diffusion under the gate which will degrade short channel effects, since the straggle effectively shortens the channel length. Also, the extension and halo implants may amorphize the material of the FinFET. That is, the high energy of the dopant used during the ion implantation process will cause displacement of the silicon atoms from the lattice structure thereby damaging the fin Si. Although amorphization reduces problems with metal diffusion that can occur during salicide formation anneal process, the amorphization-related defects are known to impede a subsequent epitaxial growth on the fin due to a decrease in the integrity of the material. For this reason, the external resistance of the FinFET can be impaired due to the difficulty in the epi growth merge process, which would otherwise increase the area of the FinFET and, in turn, reduce the external resistance of the FinFET.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.